1. Field of Invention
This invention relates to a method of forming a metal interconnect structure for integrated circuits and more particularly to such a method wherein the interconnect structure is formed by anodizing aluminum.
2. Description of the Prior Art
In the formation of integrated circuit chips, the electrical interconnections between the various elements on the wafer can be formed by depositing aluminum over the respective chips and then anodizing the aluminum in a particular pattern so as to form the respective conductor circuits between the elements. In the anodization process, a barrier layer of aluminum oxide is formed over the aluminum and a photoresist pattern is then formed over the barrier layer utilizing standard photolithographic techniques. The barrier layer prevents the formation of hillocks in the aluminum during later processing. The barrier layer is then etched away in those areas where there is no photoresist pattern, and those portions of the aluminum layer thus exposed are then subsequently anodized to form the insulating areas that define the conductive circuit patterns. Such prior art techniques are disclosed, for example, in the Gibbs et al U.S. Pat. No. 4,045,302.
Memory cells for electrically alterable read-only memories may be formed on top of the integrated circuit structure, which cells are formed of amorphous semiconductor materials which are capable of being switched to and from a low resistance crystalline state. The particular type of memory switching amorphous semiconductor material is the tellurium based chalcogenide class of materials. Such an amorphous memory device is described, for example, in the Bluhm U.S. Pat. No. 4,115,872.
A particular problem in making electrical contact with such an amorphous material is that it will interdiffuse with the aluminum conductive material during the fabrication, or during the electrical write operation after the device has been fabricated. Thus, in the prior art fabrication of such devices, a refractory material must first be placed over the conductor at those positions where contact is to be made. This requires additional lithographic and other processing steps which increase the time and cost of fabrication.
It is then, an object of the present invention to provide an improved method of making a conductor structure.
It is another object of the present invention to provide an improved method of making an electrical conductor structure for employment with integrated circuit chips.
It is still a further object of the present invention to provide an improved method of making a conductor structure that can make electrical contact with amorphous semiconductor materials.